1. Field of the Invention
The present invention relates to an array substrate and particularly to a thin film transistor array substrate.
2. Description of Related Art
Generally speaking, a liquid crystal display panel is mainly formed of a thin film transistor array substrate, a liquid crystal layer, and a color filter substrate. During the fabrication of a thin film transistor array substrate, a plurality of pixel arrays are usually simultaneously formed on a substrate, and testing circuits are timely and appropriately formed on the substrate to correspond to the pixel arrays, wherein the main function of the testing circuits is to apply a testing voltage to each pixel array, so as to detect whether the pixels in the pixel arrays function is well. After the test on the pixel arrays is completed, a laser cutting process is usually adopted to electrically separating the testing circuits from the pixel arrays, such that the pixel arrays may function properly.
To omit the aforesaid laser cutting process, the conventional technology usually adds a plurality of thin film transistors onto the testing circuits, so as to control the array test by turning on or turning off the thin film transistors. For instance, when a positive driving voltage is applied to the thin film transistors, the thin film transistors are turned on to perform the array test; and when a negative driving voltage is applied, the thin film transistors are turned off to break the testing circuits and allow the pixel arrays to function properly. After the array test is completed, the negative voltage is applied to keep the thin film transistors turned off. Hence, it is not required to perform the laser cutting process for electrically separating the testing circuits and the pixel arrays.
FIG. 1A illustrates a schematic view of a portion of a conventional thin film transistor array substrate, and FIG. 1B illustrates a schematic cross-sectional view of an area 101 in FIG. 1A. Referring to FIG. 1A first, a conventional thin film transistor array substrate 100 includes a display area 110 and a peripheral area 120, wherein a plurality of pixel units 130 are disposed on the display area 110, and a plurality of signal lines 132 disposed on the thin film transistor array substrate 100 are electrically connected with the pixel units 130. A plurality of thin film transistors 140 are disposed on the peripheral area 120, and the terminals 132a of the signal lines 132 are electrically connected to the thin film transistors 140. To be more detailed, the thin film transistor 140 includes a common gate line 142, a plurality of channel layers 144, a plurality of drain electrodes 146, and a plurality of source electrodes 148. The channel layers 144 are arranged above the common gate line 142. The drain electrodes 146 and the source electrodes 148 are respectively disposed on the corresponding channel layers 144, as shown in FIG. 1A. Specifically, the thin film transistors 140 are turned on or turned off mainly based on the voltages applied to the common gate line 142 and the source electrodes 148. For instance, when the thin film transistors 140 are turned on, the thin film transistor array substrate 100 is ready for performing the array test; and when the thin film transistors 140 are turned off, the active device (not shown) in the display area 110 of the thin film transistor array substrate 100 is allowed to perform ordinary display function. In other words, the conventional thin film transistor array substrate 100 mainly uses the thin film transistors 140 as a switch for controlling the array testing process. Hence, the laser cutting process is not required.
However, during the fabrication of the channel layers 144, static electricity is usually accumulated in the terminals 132a and the common gate line 142 to cause electrostatic discharge effects (ESD effects) which damage a dielectric layer 150 in the area 101 to form an opening 152, as indicated in FIG. 1B. After the drain electrodes 146 and the source electrodes 148 are formed, the common gate line 142 may be electrically connected with the drain electrodes 146 through the opening 152 caused by the electrostatic discharge effects between the terminals 132a and the common gate line 142, which results in line short and reduces the electrical quality and reliability of the fabrication. Generally speaking, a method for preventing the aforesaid electrostatic discharge effects is to increase the distance between the terminals 132a and the common gate line 142. However, such a method requires more space and inevitably reduces the utilization of the space in the substrate.